1. Field of the Invention
The present invention relates to a refresh circuit and a method for refreshing, and in particular, to a self row-identified hidden refresh circuit and a method for refreshing a pseudo static random access memory (pseudo SRAM).
2. Description of the Related Art
Memory is an integral component in circuit design. Dynamic random access memory (DRAM) has the advantage of being small in size. However, a DRAM requires periodic refreshing and the 1T1C memory cells used within the DRAM require special processes for their manufacture. Static random access memory (SRAM), on the other hand, has the advantage of being easy to operate. However, the SRAM requires a larger area and the high resistance resistors of the poly load 4T memory cells used within the SRAM also require special processes for their manufacture. Consequently, a 4T pseudo SRAM because it is advantageously small and easy to operate has become the best option for general CMOS processes.
FIG. 1A illustrates the configuration of a pseudo SRAM. In FIG. 1A, the pseudo SRAM comprises a memory cell array 10, a column decoder 12, a row decoder 14, a multiplexer M1, a refresh counter 16 and a controller 18. Upon accessing the memory cell array 10, the column decoder 12 and the row decoder 14 respectively receive a column address CA and a row address RA. The decoders decode the column address CA and the row address RA to obtain driving signals for accessing the memory cell array 10. Specifically, these driving signals are then sent to bit lines B.sub.0, B.sub.0 '.about.B.sub.m-1, B.sub.m-1 ' and word lines W.sub.0 .about.W.sub.n-1 of the memory cell array 10 for accessing the corresponding memory cells. Conversely, upon refreshing the memory cell array 10, the row decoder 14 will accept a refresh signal REF generated by the refresh counter 16 and refresh the memory cell array 10 by row. The multiplexer M1 selectively sends the row address RA or the refresh signal REF to the row decoder 14. The refresh counter 16 is controlled by the control circuit 18 to periodically generate the refresh signals REF.
FIG. 1B illustrates a partial circuit of the memory cell array 10 of FIG. 1A. In FIG. 1B, the memory cell array 10 comprises word lines W.sub.0 .about.W.sub.3 and bit lines B.sub.0, B.sub.0 '.about.B.sub.3, B.sub.3 ', memory cells 1 and pre-charge transistors T.sub.0, T.sub.0 '.about.T.sub.3, T.sub.3 '. Each of the memory cells 1 is located at the intersections of the word lines W.sub.0 .about.W.sub.3 and the bit lines B.sub.0, B.sub.0 '.about.B.sub.3, B.sub.3 '. The pre-charge transistors T.sub.0, T'.sub.0 .about.T.sub.3, T.sub.3 ' are respectively serially connected to the bit lines B.sub.0, B.sub.0 '.about.B.sub.3, B.sub.3 ' and are controlled by a pre-charge signal PRE.
In accordance with the framework of FIGS. 1A and 1B, the memory cell array can be refreshed by the row in the following modes: external refresh, self-refresh and hidden refresh. FIGS. 2A to 2C are diagrams illustrating the time sequence of an external refresh, a self-refresh and a hidden refresh, respectively. In FIG. 2A, the external refresh of the memory cell array 10 is determined by a refresh request provided by an external control circuit (not shown). In FIG. 2B, the self-refresh of the memory cell array 10 is determined by a refresh request provided by an internal control circuit (not shown) at non-accessing cycles. In FIG. 2C, the hidden refresh of the memory cell array 10 is determined by adding an extra refresh execution time span to each access cycle. As can be seen from the above, the self refresh requires a forceful interrupt to refresh the memory cell array 10 when continuously accessing (no gap) the memory cell array 10 for a considerable time, thus preventing data loss. The hidden refresh will decrease the maximal operation frequency, since an extra time span for refreshing is added to each access cycle. However, the overall operation (as in an SRAM) of the hidden refresh is easier, and has the advantages of being small in area and needing low direct current.
FIG. 3 illustrates a partial access circuit of a pseudo SRAM. In FIG. 3, each memory cell 1 comprises four transistors X.sub.1 .about.X.sub.4, and the access circuit 2 comprises two buffers BF.sub.1, BF.sub.2, a column decoder 3, an inverter IN.sub.1 and a sensor amplifier SA.sub.1. In this case, an NMOS transistor can be replaced with a PMOS transistor to generate the pre-charge signal PRE. When external data D.sub.in are to be written to the memory cell 1, corresponding to a word line W.sub.1 and a pair of bit lines B.sub.x, B.sub.x ', the bit lines B.sub.x and B.sub.x ' are first driven by the external data D.sub.in (the bit line B.sub.x is driven through the buffer BF.sub.1, and the bit line B.sub.x ' is driven through the inverter IN.sub.1 and the buffer BF.sub.2). Then, the word line W.sub.1 is opened for writing the external data D.sub.in into the memory cell 1.
Upon reading the memory cell 1 corresponding to the word line W.sub.i and the bit lines B.sub.x and B.sub.x ', the bit lines B.sub.x and B.sub.x ' are first pre-charged to V.sub.DD -V.sub.TN (pre-charged by the NMOS transistor) or V.sub.DD (pre-charged by the PMOS transistor). Then, the word line W.sub.i is opened to obtain the data D.sub.out in the memory cell 1 through the sensor amplifier SA.sub.1. Upon refreshing, the pre-charge signal PRE and the word line W.sub.i must be opened simultaneously so the drain voltage of the closed transistors in the memory cell can be recovered to V.sub.DD -V.sub.TN or V.sub.DD for leakage compensation.
FIGS. 4A-4C are diagrams respectively illustrating the time sequence of a pseudo SRAM in writing, reading and refreshing modes. Upon writing in FIG. 4A, the pre-charge transistors T.sub.x and T.sub.x ' and the buffers BF.sub.1 and BF.sub.2 are first turned on by a pre-charge signal PRE and a write request Write, and the bit lines B.sub.x and B.sub.x ' are driven with the external data D.sub.in. Thereafter, the word line W.sub.i is turned on for writing the external data D.sub.in to the corresponding memory cells. Upon reading in FIG. 4B, the pre-charge transistors T.sub.x and T.sub.x ' are first turned on by the pre-charge signal PRE to pre-charge the bit lines B.sub.x and B.sub.x ' to around V.sub.DD -V.sub.TN. The word line W.sub.i is then turned on for outputting the data D.sub.out in the memory cell through the sensing amplifier SA.sub.1. Upon refreshing in FIG. 4C, the pre-charge transistors T.sub.x and T.sub.x ' are first turned on by the pre-charge signal PRE, and the word line W.sub.i is simultaneously turned on to complete the refresh.
In a pseudo SRAM, a refresh row address is typically generated by a refresh counter, hence taking a longer refresh cycle. To reduce the time needed for decoding the row address, Frenkil (U.S. Pat. No. 5,193,072) and Green (U.S. Pat. No. 5,835,401) both use a ring shift register to replace the existing refresh counters. FIG. 5A illustrates the framework of a ring shift register. In FIG. 5A, outputs of the ring shift register 16' and the row decoder 14 are selected by a multiplexer M1 and sent directly to the word lines W.sub.0 .about.W.sub.n-1 of the memory cell array 10. FIG. 5B illustrates the circuit of the ring shift register 16' in FIG. 5A. In FIG. 5B, several D-type flip-flops D.sub.1 .about.D.sub.n are connected to form a ring-shaped structure with outputs of the D-type flip-flops D.sub.1 .about.D.sub.n being synchronized with a system clock CLK and sent respectively to the word lines of memory cell array 10.
Frenkil and Green's ring shift register structure, however, refreshes only a row in each cycle. Therefore, when the frequency of the system clock CLK is too low, inadequate refresh rates may result in lost data. Conversely, when the frequency of the system clock CLK is too high, excessive refresh rates may result in unnecessary power consumption.
Accordingly, an object of this invention is to provide a self row-identified hidden refresh circuit and a method of refresh to prevent data loss and excess power consumption due to inadequate system clocks.